A low-power adaptively biased output-capacitor-free low-dropout linear regulator is designed. In order to tackle the problem that the inversion coefficients of different types of input transistors in each error amplifier stage may vary asynchronously under adaptive bias caused by mismatches in the design and process, an error amplifier comprised of the recycling folded cascode amplifier and the transconductance-boosting amplifier is proposed. The driving ability for the power transistor can also be improved by the adopted pull-push output structure. Nested Miller compensation and adaptive bias are used to solve the stability problem of output-capacitor-free low-dropout regulator and improve the current efficiency at light loads. The regulator chip is implemented in SMIC 0.18 μm CMOS process with a layout area of 0.0199 mm2. The Monte Carlo post-simulation results show that the load current range is 10 μA-100 mA, with the maximum load parasitic capacitance of 100 pF, and the quiescent current is 1 μA at the minimum load condition. The load regulation and line regulation are 3.5 μV/mA and 0.372 mV/V, respectively. The designed low-dropout regulator has the merits of low power consumption, no off-chip capacitor and small area, which in-dicates that it is a good choice as intellectual property core of the power management for system on chip.