一种优化的md5算法与硬件实现
An Optimized MD5 Algorithm and Hardware Implementation
投稿时间:2021-03-22  修订日期:2021-08-31
DOI:
中文关键词:  MD5算法  hash算法  签名和验签
英文关键词:MD5 Algorithm  hash algorithm  signature and signature verification
基金项目:湖南省战略性新兴产业科技攻关与重大科技成果转化项目 2017GK4008
作者单位邮编
王镇道 湖南大学 410000
李妮 湖南大学 410000
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中文摘要:
      MD5算法是应用非常广泛的一种hash算法,在数字签名和验签中占有重要地位,算法的效率会直接影响到签名和验签的速度。论文提出一种优化的MD5算法,采用三级加法器替代四级加法器、优化循环移位操作的方式缩短MD5算法单步运算的关键路径,并用VERILOG HDL语言进行硬件实现。通过仿真和FPGA验证,结果表明该设计硬件资源消耗少,数据吞吐量大。该设计应用于一款密码安全芯片,采用0.18μm工艺进行MPW流片,芯片面积为6mm2。时钟频率为150MHz,电压3.3V时,功耗约为10.7mW。
英文摘要:
      The MD5 algorithm is a widely used hash algorithm, which occupies an important position in digital signatures and signature verification. The efficiency of the algorithm will directly affect the speed of signature and signature verification. The paper proposes an optimized MD5 algorithm, which uses a three-stage adder to replace a four-stage adder and optimizes the cyclic shift operation to shorten the critical path of the single-step operation of the MD5 algorithm, and implements the hardware in VERILOG HDL language. Through simulation and FPGA verification, the results show that the design consumes less hardware resources and has a large data throughput. The design is applied to a cryptographic security chip, using 0.18um process for MPW tape-out, the chip area is 6mm2. When the clock frequency is 150MHz and the voltage is 3.3V, the power consumption is about 10.7mW.
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