Abstract:The MD5 algorithm is a widely used hash algorithm, which occupies an important position in digital signatures and signature verification. The efficiency of the algorithm will directly affect the speed of signature and signature verification. The paper proposes an optimized MD5 algorithm, which uses a three-stage adder to replace a four-stage adder and optimizes the cyclic shift operation to shorten the critical path of the single-step operation of the MD5 algorithm, and implements the hardware in VERILOG HDL language. Through simulation and FPGA verification, the results show that the design consumes less hardware resources and has a large data throughput. The design is applied to a cryptographic security chip, using 0.18um process for MPW tape-out, the chip area is 6mm2. When the clock frequency is 150MHz and the voltage is 3.3V, the power consumption is about 10.7mW.