To meet the demands of communication base stations， radars， and other systems for high spectral purity local oscillator signals， an ultra wideband and multi functional phase-locked loop （PLL） chip was designed and implemented based on the 130 nm SiGe BiCMOS process. An off-chip test circuit system was also designed in conjunction with the chip’s application. The digital-controlled charge pump （CP） within the PLL chip can adjust crucial parameters such as loop bandwidth and system power consumption by controlling the CP current. The wideband switchable frequency divider divides the fundamental wave signal output by voltage controlled oscillator（VCO） with different operating frequency bands and performance characteristics outside the chip in the feedback loop， achieving a locked output of the fundamental wave signal in the range of 1~5.8 GHz. At the same time， an independent frequency division system integrated within the chip further expands the locking bandwidth by dividing the VCO’s fundamental wave signal output by 1/2/4/8/16， covering the output of low-frequency signals ranging from 0.15~1 GHz below the fundamental wave signal band. Tape-out testing of this PLL chip demonstrates a phase noise of -105.8 dBc/Hz at 100 kHz within the loop bandwidth for a fundamental wave output of 2.4 GHz， with a reference spur suppression of -86.12 dBc. Powered by 3.3 V， the chip can achieve a maximum phase detection frequency of 75 MHz and operate normally between -55 °C and +85 °C， providing high spectral purity local oscillator signals.