In response to the issues of high hardware resource consumption and slow processing speed associated with traditional digital interpolation filters， a design methodology based on operand resource reuse is proposed to enhance digital interpolation filter performance. Building upon the foundation of a polyphase digital interpolation filter， this method optimizes the filter architecture to enable the reuse of core computational resources， resulting in a significant reduction in circuit resources and power consumption. A novel architecture filter proposed in this study is prototyped verified on an FPGA platform，and comparative analyses are conducted with traditional interpolation filters， multi-channel parallel interpolation filters， and polyphase interpolation filters. The results indicate that the improved filter requires 65% fewer registers compared to the traditional structure， 73% fewer registers compared to the multi-channel parallel structure， and 28% fewer registers compared to the polyphase structure， respectively. The maximum operating clock frequency is increased by 129% compared to the traditional structure and 13.8% compared to the multi-channel parallel structure. Moreover， power consumption is lower than that of traditional structure and multi-channel paralle structure， making it more suitable for high-speed and low-power consumption applications.