A 10 GHz low phase noise spread spectrum clock generator(SSCG) based on a fractional PLL in a 55 nm CMOS process was developed.The clock generator adopts a LC tank voltage-controlled oscillator (VCO) with switched capacitors array to obtain the wide-band frequency range and low gain, and the multi-stage noise shaping(MASH) modulating technology was utilized to shape and degrade in-band phase noise.The SSCG changes the division ratio with triangular modulation to achieve the goal of 5 000×10-6 spread spectrum clock.The measurements show that the clock generator operates at a 10 GHz, the peak reduction of electromagnetic interference (EMI) is 16.46 dB and the phase noise is -106.93 dBc/Hz@1 MHz in Spread Spectrum Clocking (SSC) Mode.The chip core area is less than 0.28 mm2 and the core power consumption is 17.4 mW at a supply of 1.2 V．