This paper designed a NMOS ESD protection circuit with low trigger voltage (trigger voltage ≤10 V) and high ESD robustness (HBM ESD level≥4 kV).It raises the bias voltage of both the gate and the substrate of the main discharge element to an appropriate extent by designing a gate-coupled RC-network with voltage-clamping function.This not only provides a stronger discharge capacity and lower trigger voltage but also maintains a high secondary breakdown current.In this case, the ESD robustness of the MOS protection structure in CMOS deep submicron circuit is strengthened.The design is taped out in CSMC HJ018 process, and tested through TLP platform, which shows the trigger voltage is lower than 10 V and the secondary breakdown current is 3.5 A.