Considering the reliability and power consumption problems of (Field Programmable Gate Array)FPGA in aviation and spaceflight application, a new design method of low power and fault-tolerance finite state machine suitable for FPGA has been proposed. Different from traditional occupying routing resources, looking up tables and registers, this method was realized by mapping finite-state machines into the embedded blocks RAM of FPGA and employing two RAM blocks to compose the duple-redundancy structure to confirm data errors in RAM by comparing the consistency of the two blocks RAM output data and combining the parity check for error detection and correction. The experiment results have shown that this method has the advantages of lower power and higher reliability, and can achieve an error on-line error correction, compared with traditional triple-redundancy methods