The MD5 algorithm is a widely used Hash algorithm，which occupies an important position in digital signatures and signature verification. The efficiency of the algorithm will directly affect the speed of signature and sig? nature verification. This paper proposes an optimized MD5 algorithm，which uses a three-stage adder to replace a four-stage adder，optimizes the cyclic shift operation to shorten the critical path of the single-step operation of the MD5 algorithm，and implements the hardware in VERILOG HDL language. Through simulation and FPGA verifica? tion，the results show that the design function is correct and consumes fewer hardware resources and has a large data throughput. The design is applied to a cryptographic security chip，which uses a 0.18 μm process for MPW tape-out with a chip area of 6 mm2. When the clock frequency is 150 MHz and the voltage is 3.3 V，the power consumption is about 10.7mW.