Aiming at the development trend of integrated circuits (ICs ) with rapid increase in scale and power consumption, a novel capacitor-less low-dropout linear voltage regulator (CL-LDO) has been designed to provide a wide range of load currents. To solve the issues of stability and transient response caused by the requirements of wide range of load current and no off-chip capacitor, a dynamic zero-point compensation method and a transient-enhancement circuit structure have been proposed, which not only ensures the stability of the whole circuit in the full load range, but also achieves excellent transient characteristics. Based on 0.11μm CMOS technology, the circuit design, layout design and simulation are completed. The simulation results show that the overall loop gain can reach 68dB with a minimum phase margin of 56° within the load range of 0 to 500mA, the output overshoot and undershoot are 64mVand 140mV, and their settling time is 2μs and0.78μs, respectively during load current transients range from 1mA to 500mA (t=500ns), the power supply rejection (PSR) is -67dB@1kHz, the? load regulation rate is 0.136‰.