To meet the requirements of the readout circuit for the photodiode array in a digital X-ray system, a high-precision Pipelined-Successive Approximation Register (SAR) ADC has been designed. It features a gain-enhanced amplifier structure with a pre-amplification stage to improve the speed of the residue amplifier. The use of the Least Significant Bit (LSB) averaging noise-resistant method simplifies the structure of the second-stage comparator, reducing overall system power consumption. The comparator clock is self-adjusted using a feedback loop based on a Delay-Locked Loop (DLL), enhancing asynchronous timing robustness. The ADC circuit design, layout, and post-simulation verification were completed using the 0.18um EPI BCD process. Operating at a 5V supply voltage and 5MSps sampling rate, the ADC achieves an ENOB of 15.61 bits, a SNDR of 95.73dB, and a SFDR of 110.72dB.