ZHOU Hong-wei1, ZHANG Li-xia2, DOU Qiang1, LI Yong-jin1, YAN Xiao-bo1, ZHANG Ying1
(1.College of Computer, National Univ of Defense Technology, Changsha, Hunan 410073, China;2. College of Information Science and Engineering, Central South Univ, Changsha, Hunan 410083, China) 在知网中查找 在百度中查找 在本站中查找
A 2 GHz network-on-chip communication unit for multi-core microprocessors was proposed. A 2 GHz frequency in 45nm process technology can be reached and the pipeline stage is 2. There are eight bi-direction communication ports totally and the peak bandwidth is 32 GBps in each port. A test environment for network-on-chip which supports 16 high-performance processor cores was built. The test results show that network-on-chip constructed by the proposed communication unit can meet the requirements of network bandwidth by 16-core processor storage system. In the case that memory access is optimized, the aggregate bandwidth can be increased linearly with the number of the processor and thread increase. In addition, the communication unit has reusable features and can continue to be used for network-on-chip in many-core processor when it will be optimized and expanded in future. The idea of this paper has been used successfully in one of self-designed 16-core high performance microprocessors. The frequency of network-on-chip logic has been reached to 2 GHz.
