A 10-bit，150Msamples/s pipelined ADC is presented. The power of the ADC can be reduced by using dynamic comparators. The ADC has high dynamic performance when the input frequency is higher than the sampling frequency by using a bootstrap switch in the sample and holding amplifier (SHA). The ADC is fabricated in a TSMC 0.25 μm CMOS process and the active area is 2.8 mm . The measured integral and differential nonlinearity errors of the ADC at the full sampling rate are less than 1.15 LSB and 0.75 LSB, respectively. At the sampling rate of 150 MSample/s, it achieves a peak SFDR of 52.4 dB for an input frequency of 80 MHz. The power dissipation is 97 mW.