To address the design and optimization of Networks-on-Chip (NoC), a multi-FPGA based NoC emulation platform was proposed to speed up the functional verification and performance evaluation of NoC. By introducing hierarchical design approach and distributed traffic manager, the system flexibility is effectively improved while accelerating design space exploration (DSE) of NoC. The experiment result shows that the proposed emulation platform not only has a speedup of 500~10 000 times compared with classic software-based simulation method, but also outperforms other NoC platforms in emulation speed.