A multi-core system was designed based on the message-passing programming model. Within a 4×4 2D mesh Network on-Chip (NoC), this system integrated 16 small RISC processors, each equipped with a configurable private SRAM for instruction and data storage. Inter-processor packet communication was conducted via the wormhole switching routers and network interfaces. At the software level, some basic routines for data exchanging and process synchronization were implemented. Besides, 3 applications were designed by using SPMD parallel pattern for system verification and performance analysis. Simulation and FPGA test has shown that, for integer matrix multiplication, floating point FFT computation and template matching of gray images, this multi-core system can achieve a speed up to 7.6, 10.5 and 15.9 respectively.