In physical design, local high density issue always results in place and routing congestion problems. This paper presented a method of controlling chip density based on grid division in order to alleviate the drawbacks of congestion-driven optimizations by EDA tools. This paper used Synopsys IC Compiler as major experiment tool, divided the design block into several grids, and analyzed the layout-density information within each grid to control and optimize the possible congestion areas. Meanwhile, the design timing has also been improved. The effectiveness and feasibility of this strategy has been verified with actual project examples.