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A FPGA Design and Implementation of Low-complexity Decoder for LDPC Code
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    Abstract:

    Taking advantage of the good approximation performance of Chebyshev polynomial, this paper proposed a BP algorithm based on Chebyshev polynomial fitting. And this method can transform the complicated index formula into polynomial, which can reduce the consumption of memory resources. At the same time, a Chebyshev structure with shift operation was proposed to reduce the complexity brought by multiplier; also a semi-parallel architecture with pipeline design was proposed to reduce the complexity of BP decoder. The experimental results show that such a structure can effectively reduce the hardware resources.

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