This paper studied the key techniques of designing and simulating cache access time in deep sub-micron and 3-dimension era, and simulated the cache with different capacity, associativity and storage technology. The results show that, in 40nm technology, the interconnect network is a main source of the access time (up to 61.1%); the tag comparator can affect the cache access time for about 9.5%. This paper improved the existing cache access time model in which tag comparator gets insufficient attention. Based on the growing trend of the large last level cache (L3C) capacity in multi-core processors, the advantages of eDRAM on power and area make it more attractive. The simulation shows that, for L3C with large capacities (1MB, 4MB and larger than 16MB), the access time of the eDRAM cache is less than the SRAM cache for 8.1% (1MB) to 53.5% (512MB), supporting that eDRAM is a better choice for LLC in future 3D multi-core processors.