At present, the read latency of input buffer in switch is increasing, which greatly decreases the throughput of crossbar. To address this issue, a multi-VC shared prefetch structure was proposed in order to hide the read latency of data buffer implemented by SRAM with registered output. Some critical functions of SPB were designed, such as bypass write control, the management of write and read address, prefetch control, etc. Moreover, the SPB structure was implemented in Verilog and its performance was tested by cycle accurate simulator. The simulation results and analysis show that input buffer with SPB structure will not only decrease the read and write latency but also increase the throughput of the input buffer. The SPB structure proposed can be used in combination with either SAMQ or DAMQ buffer to speed up the read and write operation of the buffer, and further improve the throughput of the whole switch.