With the development of VLSI technology, the communication overhead of functional units of the full-connected network for full-distributed VLIW has become a bottleneck restricting the increase in processor frequency and scale. Based on the analysis on the characteristics of the application and 5 defined communication models, a variety of partial-connected architectures for fully-distributed VLIW were presented. The difference between partial-connected and full-connected architectures was analyzed and the related compilation modulation was accomplished, especially function unit designation and communication scheduling. Model analysis and experimental data show that, compared with full-connected architecture, partial-connected architecture can substantially reduce area and power consumption and resource overhead, and gain considerable scalability, while program performance is slightly lower.