This paper presented a design and implementation study of a three-order all-digital MASH Σ-Δ modulator, which can be used in Fractional-N Frequency Synthesizer applications. To achieve the desired operation frequency while providing low-power dissipation and small area, the pipelining technique was utilized in the design. The circuit was described by using the Verilog hardware description language, and the operating frequency of the modulator is 240.56 MHz based on QuartusⅡ. Eventually, the SMIC 0.18 μm CMOS process was adopted, and the circuit layout was completed. The chip's area is 34148.5 μm2, and the total power of the chip is 1.28 mW. Compared with traditional design, it can result in a 31.23% area reduction and 46.14% power reduction.