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Design and Implementation of Efficient Switching in Low-latency Router
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    Abstract:

    Switch allocation is a critical stage of router pipelines for On-Chip Networks, whose performance influences the overall performance of a router and even the whole NoC greatly. However, the existing time-series based switch allocation mainly is considered in canonical five-pipeline router architecture, and the researching in low-latency router is absent. So this paper made the first attempt to implement the time-series based switch allocation in low-latency router, and made improvement based on the construction features of priority matrixes in switch allocating. Simulation experiments results show that the combining time-series switch with low-latency router can greatly improve the performance of state-of-the-art NoCs.

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  • Received:
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  • Online: April 23,2015
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