As manufacturing technology for Integrated Circuit (IC) enters into 28nm technology node， the number of transistors on chip keeps on growing dramatically all the time，and interconnect delay has become one of the major obstacles of timing closure for IC designs. This paper proposed a physical-aware long-interconnect optimization methodology. The main idea of the proposed methodology is that: key cells/elements for long-interconnect delay optimization are identified and placed at place stage in EDA tools; And then，timing delay is optimized by adding/deleting buffer cells. The proposed methodology provides a solution to the problem of long-interconnect optimization issue for VLSI design in EDA tools. Experimental results indicate that:1) the quantity of buffers to be inserted can be guided by the interconnect distance between the key elements and optimized according to the specific design requirements，and using ×8 buffer between the distance in 200 μm and 250 μm can obtain the most effective effect;2) substituting the buffers with inverter-pairs can reduce the total interconnect delay dramatically by 10%; 3) using wide metal can further reduce interconnect delay for 20~30 ps.