The arbiter architecture of the ring bus was studied, and a novel extensible pipelined design was proposed, which can allocate the communication buffers and links simultaneously. Three characteristics have been found in the proposed design. Firstly, the arbiter is fair for each node, only with a 5% difference of the hit number. The communicated nodes were found in the simulation when the arbiter in an interconnect system was modeled with 14 nodes. Secondly, compared with the crossbar design, the worst time delay of our synthesis RTL design with Chartered 65 nm Technology was reduced by 36.8%. Furthermore, as the number of the nodes has less effect on the key circuit, the arbiter has certain scalability.