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A Design for High-performance Digital Output I/O Circuit
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    Abstract:

    In the digital output port of the traditional multi-power system, there are pull-up-drop-down competition and serious asymmetry between positive edge and negative edge, which results in a large delay-power product, while the large voltage fluctuation and spurious triggering result in a high SSN noise. To deal with these problems, this paper proposed a novel output circuit architecture, which employs a quick voltage level transform circuit to reduce the delay-power product and a resistance of ground bounce output structure to reduce the SSN noise. The output circuit was fabricated by SMIC18mmrf process, and the test shows that the delay-power consumption product is reduced by 5%~15% and SNN noise amplitude is lowered by 30%, compared with the traditional circuit, which indicates the high performance of the novel output circuit.

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  • Received:
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  • Online: October 29,2015
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