This paper proposed a novel phase detector structure that prevent the effect of metastability,and using a inverted delay line structure to reduce its area.The structure was implemented in SMIC 65 nm low leakage tech node inside an all digital DDR PHY which can work in frequency from 100~400 MHz.The total area is 4 298 μm2 and the DLL has a area of 2 350 μm2,chip testing results shows the IP works as expected.And since its all digital,the design also has good transplantability.