In order to deal with the problems of redundant and failed coverage in the traditional random stimuli for cache coherence verification, a high level structural stimuli generation algorithm and the corresponding functional coverage model were presented. Firstly, conflict memory accesses were categorized into basic/complex synchronizations, and thus abstracted into general bipartite graph model. Consequently, a general layered equivalence partition algorithm of ISS and the corresponding high level HSPC (Host Slave Pair Coverage) functional coverage model were proposed. Finally, two structural stimuli generation algorithms based on the search of ISS tree were presented. Experiments were performed in the functional verification of the cache system of IME-Diamond SoC, and the result indicates the HSPC coverage model can help uncover functional bugs more easily when compared with code coverage, and structural stimuli generation can reduce 96.3% stimuli for coverage convergence when compared with random stimuli generation.