In order to deal with the problem of harmonic look in the traditional Delay Locked Loop (DLL), a DLL-based 90°phase-shifter with a Schmitt Frequency Selector（SFS） was proposed. The SFS and dual delay lines were employed to achieve wider locking frequency range. In addition, the proposed SFS exhibits high capability of frequency noise suppression, which improves the stability of the proposed phase-shifter. The proposed phase-shifter, fabricated in SMIC 55 nm CMOS technology, occupies an active area of 0.131 mm2 and utilizes a 1.2 V supply voltage. The test results show that the proposed phase-shifter has an operating frequency ranging from 250 to 800 MHz and consumes 5.98 mW at 800 MHz. Furthermore, the measured peak-to-peak and root-mean-square (rms) jitters of 90°phase-shifted clock are 25.9 and 2.8 ps, respectively.