A front-end circuit without Sample-and-Hold Amplifier（SHA） is presented for reducing power consumption and increasing input range of pipelined ADC. Removing Sample-and-Hold Amplifier and improving switching timing reduce the circuit power consumption，while improving the traditional switched-capacitor comparator inputs to make ADC achieve a 0-3.3V full supply voltage quantization range. The front-end circuit without Sample-and Hold Amplifier is verified in a low power 12 bit 50 MS/s pipelined ADC. The circuit is implemented in a 0.18 μm 1P6M process，and occupies a chip area of 1.95 mm2. The test results with a 5.03 MHz input wave under a sampling rate of 50 MS/s show that the ADC achieves a 64.67 dB signal-to-noise and distortion ratio（SNDR） as well as a 72.9 dB spurious-free dynamic range（SFDR），while it consumes the power consumption of 65 mW.