To achieve the accurate output direct-current（DC）offset cancellation with fast response to the change of input DC offset introduced by the gain adjustment in the zero-intermediate-frequency receiver，a hybrid DC offset cancellation circuit is proposed. The circuit combines the advantages of analog and digital DC offset cancel? lation technology，minimizing the output residual DC offset and reducing the response time. The analog DC offset cancellation can automatically eliminate the input DC offset at each stage in real time，and the digital DC offset can? cellation further reduces the final output DC offset of the receiver by automatic calibration. An I/Q mismatch calibra? tion circuit is also proposed to automatically calibrate the I/Q gain mismatch of the zero-intermediate frequency re? ceiver. The programmable gain amplifier（PGA）circuit with the proposed DC offset cancellation and the gain mis? match automatic calibration circuit are fabricated in 65 nm CMOS process. The measurement results show that the maximum output DC offset of the PGA is 2 mV and the gain adjustment is strictly monotonic. The output I/Q gain mis? match after automatic calibration is less than 0.1 dB. The circuit has fast response time and only needs power-on cali? bration without the involvement of digital baseband circuit. The performance of the circuit fully meets the system re? quirements of wideband communications such as IEEE 802.11ax-2021 receiver.