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Design of Reference Model for Core’s Verification Based on Reduced Instruction Set
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    Abstract:

    Functional verification can find defects quickly at a low cost in the early stage of chip design,which is of great significance to ensure design quality. In view of the problems of poor instruction sequence randomnes, cumbersome testcase writing and the verification platform’s poor reusability in core module-level verification,an 8- bit RIS core verification reference model is designed. The model satisfies the verification requirements of the instruc? tion sequences’random combination and reusability through independent modeling of the instruction set and configu? rable parameter design,and the use of automated scripts solves related problem above. The reference model equipped with the UVM platform is applied to verify an 8-bit MCU core with a RISC architecture. The results show that the UVM platform integrated with the designed reference model has good robustness and reusability,the number of defects converges quickly,and the verification cycle is shorter. The code coverage and function coverage of the core module reach 100%.

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  • Received:
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  • Online: June 23,2022
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