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Design of Successive Approximation ADC Based on Ground Sampling Technique

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    To meet the requirements of power consumption and area for the output signal quantization of the flexible piezoresistive sensor, this paper presents a low-power successive approximation (SAR) analog-to-digital converter (ADC).The monotonic switching method based on the ground sampling technique minimizes DAC switching energy, while a split-capacitor DAC achieves low power in an area efficient manner. In addition,a comparator using a two-stage dynamic preamplifier was proposed to diminish the offset and noise. And dynamic element matching (DEM) techniques are employed to enhance linearity.Circuit design and layout drawing of the proposed SAR ADC were realized in 0.18 μm 1P6M CMOS technology,which occupies an active area of 630 μm× 575 μm. The SAR ADC consumes 25.7 μW at 1.8 V supply voltage.The measurement results at a sampling rate of 250 kHz show that this 11-bit ADC achieves a signal-to-noise- and-distortion ratio (SNDR) of 65.0 dB and an efficient number of bits (ENOB) of 10.51 bit.

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  • Online: March 06,2023
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