As the feature size of integrated circuits approaches the physical limit， through-silicon-via-based three-dimensional integrated circuits （3D ICs） have become a trend to continue Moore’s Law. However， existing EDA tools， technology libraries and design methodologies are far from mature enough to achieve timing convergence of ultra-large-size interposers of 3D ICs. To address this issue， a new implementation flow for physical design of TSV-based 3D ICs using conventional EDA tools is proposed. Firstly， a thermal stress model is employed to project the silicon vias into 2D blockages， thereby dividing the entire 3D IC into several 2D ICs with blockages. Each of these 2D ICs can be implemented by traditional EDA tools， respectively. Secondly， to address the timing convergence difficulties of ultra-large-size interposers， this paper puts forward a new method， which first creates a couple of bounds throughout the layout and then iteratively moves pipeline cells affecting timing greatly between the bounds. Cells in bounds are not permitted to move during placement. This approach ensures a more organized initialization and reduces disorder， thus enabling convergence to be achieved. The whole flow is applied to the physical implementation of a practical 3D integrated circuit. The experimental results show that the proposed flow can optimize both the worst negative slack and the total negative slack by more than 98% compared with the original flow. Consequently， timing convergence is accomplished， and the feasibility of the proposed design flow is proved.