A low-latency high-throughput Dynamic Virtual Output Queues Router for On-chip interconnect networks is proposed in this paper， which can reduce the router latency to two cycles by leveraging look-ahead routing computation and virtual output queues scheme. The simulation results show that， compared with the wormhole router and virtual-channel router， the network throughput on a 4×4 mesh increases by up to 46.9% and 28.6%， respectively， and outperforms doubled buffer virtual channel by 1.9% under the same input speedup. Under random synthetic traffic， the zero-load-latency of the network on chip is also reduced by 25.6% and 41%， respectively. Synthesis results indicate the frequency of router can reach 2.5 GHz.