With the advancement of integrated circuit manufacturing technology and the improvement of chip integration，the demand for low-power chips has been steadily increasing. The clock network is responsible for more than 40% of the total power consumption of the chip. Consequently， optimizing the power consumption of the clock network has become one of the most important goals in the design of high-performance integrated circuits. In this paper， a new register clustering method is proposed to generate the leaf level topology of the clock tree. By carefully limiting the fan-out， load， and range of the clusters to reasonably group the registers， the method effectively reduces the number of buffer insertions and the total wiring length， and the clock network power consumption is also significantly reduced. The method is integrated into the traditional clock tree synthesis （CTS） flow， and its effectiveness is tested and analyzed on the ISCAS89 benchmark circuit. Experimental results show that the register clustering method effectively reduces the power dissipation of the clock network by more than 20% and the clock offset by more than 20%， without affecting the maximum delay of the clock tree.