Aiming at the development trend of integrated circuits （ICs） with rapid increase in scale and power consumption， a novel capacitor-less low-drop-out linear voltage regulator （CL-LDO） has been designed to provide a wide range of load currents. To solve the issues of stability and transient response caused by the requirements of a wide range of load currents and no off-chip capacitor， a dynamic zero-point compensation method and a transient enhancement circuit structure are proposed， which not only ensures the stability of the whole circuit in the full load range， but also achieves excellent transient characteristics. Based on 0.11 μm CMOS technology， the circuit design， layout design and simulation are completed. The simulation results show that the overall loop gain can reach 68 dB with a minimum phase margin of 56° within the load range of 0 mA to 500 mA， the output overshoot and undershoot are 56 mVand 141 mV， and their settling time is 2 μs and 0.78 μs， respectively， when load current transients range from 1 mA to 500 mA （Δt=500 ns）， the power supply rejection （PSR） is -67.2 dB@1 kHz， and the load regulation rate is 0.137 μV/mA.