To meet the requirements of the readout circuit of the photodiode array in the digital X-ray system for an analog-to-digital converter （ADC） with superior average performance， a high-precision pipelined-successive approximation register analog-to-digital converter is designed. It features a gain-enhanced amplifier structure with a pre-amplification stage to realize the high efficiency amplifier. The use of the least significant bit （LSB） averaging noise-resistant method simplifies the structure of the second-stage comparator， effectively reducing overall system power consumption. The self-adjusted comparator clock is also realized using a feedback loop based on a delay-locked loop （DLL）， enhancing asynchronous timing robustness. The ADC circuit design， layout， and post-simulation verification were completed using the 0.18 μm EPI BCD process. Under 5.0 V supply voltage and 5 MS/s sampling rate conditions， the ADC achieves an ENOB of 15.61 bits， an SNDR of 95.73 dB， and an SFDR of 110.72 dB.