This paper proposed an improved hierarchical flow for physical design in deep sub-micron technology. This flow can reduce routing congestion and improve timing delay. The key point of this flow is to use the external connectivity information of the target block to design the floorplan, which could achieve a good place and route result in one iteration using quantitative analysis, saving time and efforts from multiple failed iterations. The proposed flow was tested on a large mux block in DSP design in SMIC 65nm low leakage process, result shows it improved 20% in area and 35% in timing delay comparing to tradition flow.